i working in xilinx webpack vhdl , nexys 2 fpga , trying used making modular code. project consists of 3 short files: main.vhd, adder_4bit.vhd, , constraints.ucf. code compiles fine led 6 lights , nothing responds changes switches supposed to. here files:
main.vhd
-- arithmetic functions signed or unsigned values --use ieee.numeric_std.all; -- uncomment following library declaration if instantiating -- xilinx primitives in code. --library unisim; --use unisim.vcomponents.all; entity main port ( switches : in std_logic_vector (7 downto 0); leds : out std_logic_vector (7 downto 0)); end main; architecture behavioral of main component adder_4bit port( x : in std_logic_vector(3 downto 0); y : in std_logic_vector(3 downto 0); cin : in std_logic; cout : out std_logic; sum : out std_logic_vector(3 downto 0); gp : out std_logic; gg : out std_logic ); end component; signal 0 : std_logic; begin inst_adder_4bit: adder_4bit port map( x => switches(7 downto 4), y => switches(3 downto 0), cin => zero, cout => leds(7), sum => leds(3 downto 0), gp => leds(6), gg => leds(5) ); leds(4) <= '0'; end behavioral; adder_4bit.vhd
-- uncomment following library declaration if using -- arithmetic functions signed or unsigned values --use ieee.numeric_std.all; -- uncomment following library declaration if instantiating -- xilinx primitives in code. --library unisim; --use unisim.vcomponents.all; entity adder_4bit port ( x : in std_logic_vector (3 downto 0); y : in std_logic_vector (3 downto 0); cin : in std_logic; cout : out std_logic; sum : out std_logic_vector (3 downto 0); gp : out std_logic; gg : out std_logic); end adder_4bit; architecture behavioral of adder_4bit signal p : std_logic_vector (3 downto 0); signal g : std_logic_vector (3 downto 0); signal icarry : std_logic_vector (4 downto 0); begin p <= x or y; g <= x , y; icarry(0) <= cin; icarry(1) <= g(0) or (p(0) , icarry(0)); icarry(2) <= g(1) or (p(1) , icarry(1)); icarry(3) <= g(2) or (p(2) , icarry(2)); icarry(4) <= g(3) or (p(3) , icarry(3)); sum(0) <= x(0) xor y(0) xor icarry(0); sum(1) <= x(1) xor y(1) xor icarry(1); sum(2) <= x(2) xor y(2) xor icarry(2); sum(3) <= x(3) xor y(3) xor icarry(3); cout <= icarry(4); gp <= p(0) , p(1) , p(2) , p(3); gg <= g(3) or (g(2) , p(3)) or (g(1) , p(2) , p(3)) or (g(0) , p(1) , p(2) , p(3)); end behavioral; and constraints.ucf
net switches(7) loc = "r17"; net switches(6) loc = "n17"; net switches(5) loc = "l13"; net switches(4) loc = "l14"; net switches(3) loc = "k17"; net switches(2) loc = "k18"; net switches(1) loc = "h18"; net switches(0) loc = "g18"; net leds(7) loc = "r4"; net leds(6) loc = "f4"; net leds(5) loc = "p15"; net leds(4) loc = "e17"; net leds(3) loc = "k14"; net leds(2) loc = "k15"; net leds(1) loc = "j15"; net leds(0) loc = "j14"; #net lcd_a0 loc = "f17"; #net lcd_a1 loc = "h17"; #net lcd_a2 loc = "c18"; #net lcd_a3 loc = "f15"; #net lcd_a loc = "l18"; #net lcd_b loc = "f18"; #net lcd_c loc = "d17"; #net lcd_d loc = "d16"; #net lcd_e loc = "g14"; #net lcd_f loc = "j17"; #net lcd_g loc = "h14"; #net lcd_dp loc = "c17"; #net clock loc = "b8"; #net "clock" tnm_net = clock; #timespec ts_clk = period "clock" 4 ns high 50%; thanks in advance.
i not have access synthesiser right now, believe problem have not initialised 0 value.
when signal not defined, optimizer might optimize things out did not intend.
try declaring 0 signal constant or wiring cin '0'.
(i have left comment, seems need more rep that)
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