in synthesis tools fpga output of hdl synthesis kind of edif format. e.g. in synopsys such format has extension .edn. however, format fpga-technology dependent (depends on fpga-type chosen before synthesis , cells). meanwhile in synthesis tools can see gate level representation simplest or, , gates , dff, output files level of representation encrypted.
i have lowest level (and,or, dff) netlist after fpga synthesis process. since generated edif files technology/cells dependent, not easy parse them (i need library of fpga cell descriptions). can anyhow synthesis programs lowest level netlist representation?
thank in advance attention.
if want low-level gate netlist, need synthesise target library has elements. because fpgas not have raw gates within them, when synthesiser targets them, (somewhat obviously) creates elements available it.
if use asic tool, will use low level gates, target has available.
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